Summary

Date:

23 Nov 2019

Directory

Please go to tesla-cat/Works-Done-In-Dzmitry-Lab-At-CQT

  • the codes are located at Works-Done-In-Dzmitry-Lab-At-CQT/Cyclone V SoC Control System/Quartus Project Stage 3/

  • the documents are located at Works-Done-In-Dzmitry-Lab-At-CQT/Cyclone V SoC Control System/Documents/

Verilog Part

  • The cyclone V FPGA is a SoC system consists of an Arm v7 processor and a FPGA

  • I start from the DE10_NANO_SoC_GHRD folder downloaded from terasic official site. This Quartus project provides a template to build on top of.

  • I then defined PIO ports provided by the Platform Designer in Quartus, the PIO ports can be accessed by

    • the processor using C program

    • the FPGA using verilog

    • this is done via memory mapping

  • In this project I defined 4 PIOs in DE10_NANO_SoC_GHRD/soc_system.qsys

    • FIFOreadRequest: 1 bit

    • FIFOreadDataQueue: 32 bits

    • FIFOreadEmpty: 1 bit

    • requestPIO: 32 bits

    • The FIFO is used to send data from FPGA to processor

    • The requestPIO is used to handle request sent by the processor

  • Then I modify the main verilog module DE10_NANO_SoC_GHRD/DE10_NANO_SoC_GHRD.v

    • the code I added are highlighted in the following way

//OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
// Begin Code added by me Part 0: Physical Pins
 ...
// End Code added by me Part 0: Physical Pins
//OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

  • After modifying the above two existing files, I create a FIFO module using Quartus standard library

  • Finally I can focus on writing my own modules, which I am familiar with. You can find my modules in DE10_NANO_SoC_GHRD/my_modules/

    • DataSender.v : gets data from My16ChannelCounter and send them to FIFO

    • MemoryMapper.v : gets data from requestPIO and send them to My16ChannelCounter

    • My16ChannelCounter.v : gets data from pins in16Channels and send them to DataSender

    • MyMainModule.v : wraps the above up

    • ToShortPulse.v : a utility for FIFO

  • I have finished the codes, then I did physical pin mapping according to Documents/PinMap.html, then I compiled the project to generate DE10_NANO_SoC_GHRD/output_files/DE10_NANO_SoC_GHRD.sof

  • Then I modified the file DE10_NANO_SoC_GHRD/output_files/sof_to_rbf.bat and used it to convert DE10_NANO_SoC_GHRD.sof to soc_system.rbf. I then put this file in the boot partition of the SD card of the DE10 nano board. Now the verilog program will automatically run whenever the board reboots

C Part

  • I modify the example project HPS_FPGA_LED

    • first I modify HPS_FPGA_LED/main.c

    • then I make the C file into executable HPS_FPGA_LED

  • Inside the C file, 3 addresses for the FIFO are defined, they are the same as in DE10_NANO_SoC_GHRD/soc_system.qsys

  • I did not define the address for requestPIO for flexibility, instead the user will input the address as argument for the program

    • In this case the “user” would be the nodeJs program below

Javascript Part

  • First I create a class nodeJsPart/my_modules/SimpleDE10NANO.js, this class does all the work, it is a http server

  • I then create the client side script nodeJsPart/my_modules/client.html, this is only a demo of using the backend API, the counter data are plotted using plotly.js

  • Then I create the main file nodeJsPart/server.js, it automatically finds the processor’s IP address

  • Finally I copied the C executable HPS_FPGA_LED to nodeJsPart/HPS_FPGA_LED so it can be called by server.js as a child_process

  • I also had to follow Documents/terasic_de10_lab_setup.pdf to fix the IP and Mac addresses

  • Finally I typed node server.js in the console and visited 192.168.101.172:3000 from a computer connected to the same router as the DE10 Nano board

  • Everything worked and I felt happy, next I will let my boss use it in his lab and provide feedback so I may discover bugs