Processor-FPGA Communication: FPGA Part
===========================================================

:Date: 12 Aug 2019

`Corresponding Project Folder`_
------------------------------------------

.. _Corresponding Project Folder: https://github.com/tesla-cat/Works-Done-In-Dzmitry-s-Lab-At-CQT/tree/master/Cyclone%20V%20SoC%20Control%20System/Quartus%20Project/DE10_NANO_SoC_GHRD


Dependency
-------------

- `DE10 Nano Development Board Website`_
- Quartus (For FPGA part) [I am using Quartus Lite 18.1]
- C Programming (For Processor part)

.. _DE10 Nano Development Board Website: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046&PartNo=4

What is the problem ?
-------------------------

- Before Cyclone V, FPGAs I used are independent. So I used SPI, UART etc. to handle communication with Processors
- In Cyclone V, Processor (Called HPS) and FPGA are put on the same chip (Known as SoC)
- So we use a communication interface with much better performance: AXI (Advanced eXtensible Interface)
- The key to AXI is the share of memory

FPGA Part
--------------------------------

**Step 1** AXI Bridge Block Diagram

.. figure:: imgs/7-1_AXI_Bridge_Block_Diagram.webp

**Step 2** To design the entire system from scratch is **hard**, We only need to modify the **Basis Design**

- Download file **DE10-Nano CD-ROM** from `DE10 Nano Development Board Website`_
- The **Basis Design** files can be found in :code:`Demonstrations\SoC_FPGA\DE10_NANO_SoC_GHRD` folder
- Open :code:`DE10_NANO_SoC_GHRD.qpf` with Quartus

**Step 3** Map **Memory Address** to **Physical Pins**

- Go to **Quartus >> Tools >> Platform Designer**
- A open file window should pop up, choose file :code:`soc_system.qsys`
- The following figures should explain themselves

.. figure:: imgs/7-2_System_Contents_^_led_pio_external_connection.webp

    At **System Contents** set the name **led_pio_external_connection**

.. figure:: imgs/7-3_Address_Map_^_led_pio.webp

    At **Address Map** define address for **led_pio**

- Now go back to **Quartus** from **Platform Designer**, open the Verilog file :code:`DE10_NANO_SoC_GHRD.v`

.. figure:: imgs/7-4_DE10_NANO_SoC_GHRD_^_FPGA_Partion.webp

    In :code:`DE10_NANO_SoC_GHRD.v` file we connect **led_pio_external_connection_export** to **fpga_led_internal**

.. figure:: imgs/7-5_DE10_NANO_SoC_GHRD_^_REG_WIRE_declarations.webp

    In :code:`DE10_NANO_SoC_GHRD.v` file we connect **fpga_led_internal** to **LED**

- Now open **Pin Planner**, refer to file `Pin Map html`_ 

.. _Pin Map html: https://github.com/tesla-cat/Works-Done-In-Dzmitry-s-Lab-At-CQT/blob/master/Cyclone%20V%20SoC%20Control%20System/Quartus%20Project/PinMap.html

.. figure:: imgs/7-6_Pin_Planner_^_LED.webp

    Here we connect **LED** to **Physical Pins on FPGA**

Now we know how to map **Memory Address** to **Physical Pins**, these **Memory Address** will be directly used in **C Programs** later

**Step 4** Generate >> TCL >> Compile >> Program

- **Platform Designer >> Generate >> Generate HDL... >> Generate**. This automatically generates Verilog files which you would have to write yourself if you don't use Platform Designer
- :code:`.tcl` files are already executed in GHRD project, so **you can skip this step**. But if the project is not based on the GHRD project: **Quartus >> Tools >> Tcl Scripts...**, select :code:`_parameters.tcl` and :code:`_pin_assignments.tcl` and Run
- **Quartus >> Processing >> Start Compilation**, :code:`DE10_NANO_SoC_GHRD.sof` will be generated :code:`output_files` folder
- Finally just use **Quartus >> Tools >> Programmer** to program the board

.. figure:: imgs/7-7_Programmer.webp